Communication - Minimizing Algorithms for Matrix Multiplication

As computers increase in speed, the proportion of time spent on communication between cache and hard drive or between multiple processors continues to rise. For single processors, data must be moved between the processor’s fast-access cache and main memory, an operation that often takes many orders of magnitude longer than any arithmetic operation. When multiple levels of cache are present, a cache-oblivious algorithm, one that will work effectively for any memory hierarchy, is desired, but designing such algorithms has proven challenging.